About: RAM Circuits

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This article presents several circuits that may be used to apply the Memory Bank as a Read/Write memory, commonly called RAM. It assumes that the memory will be attached to a common data bus for input and output. This means there must be a way to tell this circuit two things – when the data on the bus is for it, and when to output its data to another device. We still need the proper controls for the clock input to the bank as well.

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rdfs:label	RAM Circuits
rdfs:comment	This article presents several circuits that may be used to apply the Memory Bank as a Read/Write memory, commonly called RAM. It assumes that the memory will be attached to a common data bus for input and output. This means there must be a way to tell this circuit two things – when the data on the bus is for it, and when to output its data to another device. We still need the proper controls for the clock input to the bank as well.
dcterms:subject	Electricity Circuits
abstract	This article presents several circuits that may be used to apply the Memory Bank as a Read/Write memory, commonly called RAM. It assumes that the memory will be attached to a common data bus for input and output. This means there must be a way to tell this circuit two things – when the data on the bus is for it, and when to output its data to another device. We still need the proper controls for the clock input to the bank as well. When the bank is used as Read/Write memory, we must use the clock input. That means we have to deal with the ‘weirdness’ of this input. In addition to this input serving two functions, it is also edge-triggered, rather than level sensitive. That means the timing of the changes must be considered in relationship to the system timing needs. The clock input can be derived different ways depending on what control signals are available from the system. There must be at least one signal that tells it what type of access to initiate and perhaps another one that sets the timing of the access. In order to be connected to the bus, there must also be an output enable as well. These signals control data bus access and must be timed correctly for the bus interface. As is typical in any clocked system, all the address lines, the R/-W control, any other control signals and any data that must be read from the data bus are set to their required levels and allowed to settle first. Then the system clock transitions (usually to ‘1’) to initiate any action.

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