When the Z80 wishes to access an IO port, it places the port address on the address bus exactly as it does when accessing memory. On the 48K and 128K Spectrums, this causes delays to IO as the ULA halts the processor. On the +3 Spectrum, no contention occurs as the +3 ULA applies contention only when the Z80's MREQ line is active, which it is not during an IO operation. Two effects can occur here: The combination of these two effects leads to the following pattern: